1. Field of the Invention
The present invention relates to pseudo-random pattern generators (PRPGs) and in particular to increasing PRPG-based compression by modifying test generation so that a justification of certain decision nodes is delayed and merged with PRPG seed computation.
2. Related Art
Larger and more complex logic designs in integrated circuits (ICs) lead to demands for more sophisticated testing to ensure fault-free performance of those ICs. This testing can represent a significant portion of the design, manufacture, and service cost of integrated circuits (ICs). In a simple model, testing of an IC can include applying multiple test patterns to the inputs of a circuit and monitoring its outputs to detect the occurrence of faults. Fault coverage indicates the efficacy of the test patterns in detecting each fault in a universe of potential faults. Thus, if a set of test patterns is able to detect substantially every potential fault, then fault coverage approaching 100% has been achieved.
To facilitate better fault coverage and minimize test cost, DFT (design-for-test) can be used. In one DFT technique, structures in the logic design can be used. Specifically, a logic design implemented in the IC generally includes a plurality of state elements, e.g. sequential storage elements like flip-flops. These state elements can be connected into scan chains of computed lengths, which vary based on the design. In one embodiment, all state elements in a design are scannable, i.e. each state element is in a scan chain. The state elements in the scan chains are typically called scan cells. In DFT, each scan chain includes a scan-input pin and a scan-output pin, which serve as control and observation nodes during the test mode.
The scan chains are loaded by clocking in predetermined logic signals through the scan cells. Thus, if the longest scan chain includes 500 scan cells, then at least 500 clock cycles are used to complete the loading process. Note that, in actual embodiments, software can compensate for different scan chain lengths, thereby ensuring that outputs from each test pattern are recognized and analyzed accordingly.
The test patterns for the scan chains can be generated using an external testing device. Using such a device, an exhaustive test can be done by applying 2N input patterns to a design with N inputs and scan cells, wherein N is a positive integer. However, this test approach is commercially impractical as the number of inputs increases.
To solve this problem, deterministic automatic test pattern generation (ATPG) can be used to generate a smaller set of patterns while providing fault coverage close to 100%. Specifically, in deterministic ATPG, each test pattern is designed to test for as many faults as possible. However, even with the reduction in test patterns, deterministic ATPG patterns still require significant storage area in the test-application equipment (tester) for the large number of patterns that are input directly to the scan chains, and for the expected output values from the scan chains. Moreover, this test method has associated inefficiencies because of its off-chip access time.
Alternatively, and more frequently in current, complex ICs, structures can be added to the design that allow the IC to quickly test itself. These built-in self-test (BIST) structures can include various pattern generators, the most typical being a pseudorandom pattern generator (PRPG). After the patterns generated by the PRPG are propagated through the scan chains in the tested design, the outputs are analyzed to determine if a fault is detected. An exemplary scan test system and technique using PRPG is described in U.S. Pat. No. 7,237,162, entitled “Deterministic BIST Architecture Tolerant Of Uncertain Scan Chain Outputs”, which issued on Jun. 26, 2007 and is incorporated by reference herein.
To achieve high defect coverage during IC scan testing, particularly in light of shrinking process technologies and new IC materials, different fault models (e.g. stuck-at, transition delay, and shorts/opens models) may be used. Unfortunately, although test patterns for timing dependent and sequence dependent fault models are increasingly important for new technologies, such test patterns can require 2-5 times more tester time and data. Current increases in test data volume and test application time are projected to continue for at least an order of magnitude for next generation tools. Therefore, scan-alone scan testing has become insufficient as a method to control test costs. Even highly compacted vector sets generated with modern ATPG require on-chip compression and decompression to reduce test cost.
Scan compression lowers test cost by reducing test pattern volume, test application time, and tester pin count requirements. Techniques described below can advantageously increase scan input data compression while maintaining test coverage, test diagnosis, and hardware support.